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general description the max3542 complete single-conversion television tuner is designed for use in analog/digital terrestrial appli- cations and digital set-top boxes. this television tuner draws only 760mw of power from a +3.3v supply voltage. the max3542 is designed to convert pal or dvb-t sig- nals in the 47mhz to 862mhz band to an intermediate frequency (if) of 36mhz. the max3542 includes a variable-gain low-noise amplifi- er (lna), multiband tracking filters, a harmonic-rejection mixer, a low-noise if amplifier, an if power detector, and a variable-gain if amplifier. the max3542 also includes fully monolithic vcos and tank circuits, as well as a complete frequency synthesizer. this highly integrated design allows for low-power tuner-on-board applications without the cost and power dissipation issues of dual- conversion tuner solutions. the max3542 is specified for operation in the 0? to +70? temperature range and is available in a lead-free 48-pin flip-chip (fclga) package. applications televisions analog/digital terrestrial receivers digital set-top boxes features low power consumption: 760mw (typ) from a +3.3v supply voltage integrated tracking filters low noise figure: 4.9db (typ) small 7mm x 7mm fclga lead-free package if overload detector controls rf variable-gain amplifier 2-wire, i 2 c-compatible serial control interface max3542 complete single-conversion television tuner ________________________________________________________________ maxim integrated products 1 ordering information 19-4337; rev 2; 4/11 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. evaluation kit available part temp range pin-package m ax 3542c lm + 0 c to + 70 c 48 lga- e p * + denotes a lead(pb)-free/rohs-compliant package. * ep = exposed paddle. pin configuration/functional diagram max3542 36 ifout1- 1 13 48 14 47 15 46 16 45 17 44 18 43 19 42 20 41 21 40 22 39 23 38 24 37 scl + 35 ifout1+ 2 sda 34 ifovld 3 v cc 33 v cc 4 uhf_in 32 v cc v ref 5 vhf_in 31 gnd 6 rfgnd2 30 ifin+ 7 lext 29 ifin- 8 rfgnd3 28 v cc 9 rfagc 27 gnd 10 v cc 26 ifagc 11 gnd 25 ifout2+ 12 gnd addr2 gnd addr1 gnd xtalp gnd xtaln gnd v cc gnd cp gnd mux gnd v cc gnd vtune gnd gnd_tune gnd ldo v cc v cc ifout2- serial interface r pd cp n vco divider ep + -
max3542 complete single-conversion television tuner 2 _______________________________________________________________________________________ absolute maximum ratings dc electrical characteristics (max3542 ev kit, v cc = +3.1v to +3.5v, t a = 0c to +70c, no rf signals at rf inputs, default register settings, v rfagc = v ifagc = +3v (minimum attenuation), unless otherwise noted. typical values are at v cc = +3.3v, t a = +25c, unless otherwise noted.) (note 1) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v cc to gnd ..............................................................-0.3v, +3.6v uhf_in, vhf_in, ifin_, ifout1_, ifout2_, ifagc, rfagc, vtune, ldo, mux, cp, xtal_ to gnd ........................................-0.3v to (v cc + 0.3v) sda, scl, addr2, addr1 to gnd......................-0.3v to +3.6v ifout__ short-circuit duration .....................................indefinite rf input power ...............................................................+10dbm continuous power dissipation (t a = +70c) 48-pin lga (derate 25mw/c above +70c) .................1.4w operating temperature range...............................0c to +70c junction temperature ......................................................+150c storage temperature range .............................-65c to +165c lead temperature (soldering, 10s) .................................+250c soldering temperature (reflow) .......................................+240c caution! esd sensitive device parameter conditions min typ max units supply voltage and current supply voltage +3.1 +3.5 v receive mode 230 275 supply current shutdown mode 5 ma rf and if ag c inp ut bi as c ur r ent at +0.5v and +3v -50 +50 a minimum attenuation +3 rf and if agc control voltage (note 2) maximum attenuation +0.5 v digital input logic-level low 0.3 x v cc v digital input logic-level high 0.7 x v cc v serial interface input logic-level low 0.3 x v cc v input logic-level high 0.7 x v cc v input hysteresis 0.05 x v cc v sda, scl input current -10 +10 a output logic-level low 3ma sink current 0.4 v output logic-level high v cc - 0.5 v
max3542 complete single-conversion television tuner _______________________________________________________________________________________ 3 ac electrical characteristics (max3542 ev kit, v cc = +3.1v to +3.5v, t a = 0c to +70c, 75 system impedance, default register settings, v rfagc = v ifagc = +3v (minimum attenuation), unless otherwise noted. typical values are at v cc = +3.3v, t a = +25c, unless otherwise noted.) (note 1) parameter conditions min typ max units rf input to ifout1_ output operating frequency range (see table 7) gain specification met across this frequency band 47 862 mhz analog channel pix carrier 38.9 output frequency digital channel center frequency 36 mhz maximum gain (v rfagc = 3v) 34 41 49.5 voltage gain source impedance = 75 , load impedance = 200 minimum gain (v rfagc = 0.5v) -10 db input return loss selected channel 10 db noise figure maximum gain (v rfagc = 3v) 4.9 db maximum gain (v rfagc = 3v) 20 input ip2 (in-band and out-of-band tones) at 12.5db of gain 30 dbm maximum gain (v rfagc = 3v) -10 input ip3 (in-band and out-of-band tones) at 12.5db of gain 13 dbm maximum gain (v rfagc = 3v) -38 input p 1db at 12.5db of gain -5 dbm beats within output 0dbmv pix carrier level -40 dbc vhf input, 140mhz to 500mhz -60 vhf input, 500mhz to 1400mhz -50 beats, converted to output uhf input, 950mhz to 1400mhz -60 dbc gain flatness 47mhz to 54mhz 2.5 db p-p isolation 5mhz to 50mhz, rf input to if output, relative to desired channel 60 dbc port-to-port isolation isolation between rf input ports at 215mhz 27 db image rejection measured at 77.8mhz above desired channels center frequency 57 70 dbc 5hz to 65mhz -40 spurious leakage at rf input 65mhz to 878mhz -40 dbmv 1khz -80 10khz offset -85 100khz offset (1.5khz loop bandwidth) -105 phase noise (single-sideband) 1mhz offset (1.5khz loop bandwidth) -125 dbc/hz output return loss balanced 50 load 20 db if variable-gain amplifier input impedance balanced 2000 output impedance balanced (note 2) 300
max3542 complete single-conversion television tuner 4 _______________________________________________________________________________________ ac electrical characteristics (continued) (max3542 ev kit, v cc = +3.1v to +3.5v, t a = 0c to +70c, 75 system impedance, default register settings, v rfagc = v ifagc = +3v (minimum attenuation), unless otherwise noted. typical values are at v cc = +3.3v, t a = +25c, unless otherwise noted.) (note 1) parameter conditions min typ max units maximum gain setting (v ifagc = 3v) 54 59 63 passband voltage gain s our ce l oad = 1.1k , output load = 1k minimum gain setting (v ifagc = 0.5v) 21 db passband gain flatness 32mhz to 40mhz (note 2) 1.2 db output voltage v ifagc = 3v (note 2) 2.5 v p-p agc gain slope v ifagc = 3v to 0.5v (note 2) 27 db/v equivalent input-voltage noise density at 36mhz, maximum gain (v ifagc = 3v) (note 2) 7.3 nv/ hz noise figure change vs. attenuation < 0.35 db/db im3 v out = 1v p-p , 40db < gain < 60db (note 2) -56 dbc if overload detector (see the if overload detector section) output overload attack point 0.7 v p-p attack point accuracy od reg = 3 1 db detector output-voltage range negative polarity, overload reduces v det (open collector, 0.3ma sink) 0.5 3.0 v detector gain 70 v/v frequency synthesizer?eference oscillator frequency 8 mhz dividers rf n-divider ratio 256 32,767 rf r-divider ratio 16 127 lo phase detector and charge pump comparison frequency 63 500 khz cp = 00 0.5 cp = 01 1 cp = 10 1.5 charge-pump current cp = 11 2 ma charge-pump three-state current 5 na charge-pump compliance range 0.4 v cc - 0.4 v charge-pump current matching 5% local oscillator vco tuning range tank frequency 2200 4400 mhz vco tuning gain tank oscillator gain 500 mhz/v 2-wire serial interface clock frequency 400 khz note 1: min/max values are production tested at t a = +70c. note 2: guaranteed by design and characterization.
max3542 complete single-conversion television tuner _______________________________________________________________________________________ 5 supply current vs. supply voltage supply voltage (v) supply current (ma) max3542 toc01 3.1 3.2 3.3 3.4 3.5 216 220 224 228 232 -40 c +25 c +85 c vhf voltage gain vs. rfagc voltage rfagc voltage (v) vhf voltage gain (db) max3542 toc02 0.5 1.0 1.5 2.0 2.5 3.0 -20 0 20 40 60 f rf = 64.5mhz +85 c -40 c +25 c uhf voltage gain vs. rfagc voltage rfagc voltage (v) uhf voltage gain (db) max3542 toc03 0.5 1.0 1.5 2.0 2.5 3.0 -20 0 20 40 60 f rf = 801mhz +85 c +25 c -40 c vhf lo voltage gain vs. frequency frequency (mhz) voltage gain (db) max3542 toc04 0 50 100 150 200 250 32 44 46 48 50 36 34 38 40 42 +55 c +25 c +70 c 0 c vhf hi voltage gain vs. frequency frequency (mhz) voltage gain (db) max3542 toc05 150 200 250 300 350 400 450 32 38 48 50 34 40 36 42 44 46 +55 c +25 c +70 c 0 c uhf voltage gain vs. frequency frequency (mhz) voltage gain (db) max3542 toc06 400 700 650 600 550 500 450 850 800 750 900 32 36 40 44 34 38 42 46 48 50 +55 c +25 c +70 c 0 c vhf hi noise figure vs. frequency frequency (mhz) noise figure (db) max3542 toc08 150 350 400 250 300 200 450 2 4 6 8 3 5 7 +70 c 0 c +55 c +25 c typical operating characteristics (max3542 ev kit, v cc = +3.3v, v ifagc = 3.0v, v rfagc = 3.0v, t a = +25c, unless otherwise noted.) vhf lo noise figure vs. frequency frequency (mhz) noise figure (db) max3542 toc07 0 50 100 150 200 250 2 4 6 8 3 5 7 +70 c 0 c +55 c +25 c
max3542 complete single-conversion television tuner 6 _______________________________________________________________________________________ typical operating characteristics (continued) (max3542 ev kit, v cc = +3.3v, v ifagc = 3.0v, v rfagc = 3.0v, t a = +25c, unless otherwise noted.) uhf noise figure vs. frequency frequency (mhz) noise figure (db) max3542 toc09 400 800 450 900 600 850 650 700 500 750 550 2 4 6 8 3 5 7 +70 c 0 c +55 c +25 c vhf noise figure vs. rfagc voltage rfagc voltage (v) noise figure (db) max3542 toc10 1.8 2.0 2.2 2.4 2.6 2.8 3.0 0 4 8 12 16 20 f rf = 224.25mhz +55 c +85 c +25 c 0 c -40 c uhf noise figure vs. rfagc voltage rfagc voltage (v) noise figure (db) max3542 toc11 1.8 2.0 2.2 2.4 2.6 2.8 3.0 0 4 8 12 16 20 f rf = 631.25mhz +55 c +85 c +25 c 0 c -40 c vhf lo image rejection vs. frequency frequency (mhz) image rejection (db) max3542 toc12 0 150 200 100 50 250 60 65 70 75 80 85 90 +70 c 0 c +55 c +25 c vhf hi image rejection vs. frequency frequency (mhz) image rejection (db) max3542 toc13 150 300 350 200 250 400 450 60 65 70 75 80 85 90 +70 c 0 c +55 c +25 c uhf image rejection vs. frequency frequency (mhz) image rejection (db) max3542 to14 400 700 650 600 550 500 450 850 800 750 900 60 65 70 75 80 85 90 +70 c 0 c +55 c +25 c
max3542 complete single-conversion television tuner _______________________________________________________________________________________ 7 typical operating characteristics (continued) (max3542 ev kit, v cc = +3.3v, v ifagc = 3.0v, v rfagc = 3.0v, t a = +25c, unless otherwise noted.) vhf phase noise at 10khz offset vs. channel frequency channel frequency (mhz) vhf phase noise (dbc/hz) max3542 toc15 45 50 55 60 65 70 -105 -103 -101 -99 -97 -95 vhf phase noise at 10khz offset vs. channel frequency channel frequency (mhz) vhf phase noise (dbc/hz) max3542 toc16 170 180 190 200 210 220 230 240 -100 -98 -96 -94 -92 -90 uhf phase noise at 10khz offset vs. channel frequency channel frequency (mhz) uhf phase noise (dbc/hz) max3542 toc17 400 500 600 700 800 900 -95 -92 -89 -86 -83 -80 vhf phase noise vs. offset frequency offset frequency (khz) vhf phase noise (dbc/hz) max3542 toc18 -140 -120 -100 -80 -60 0.1 1 10 100 1000 f rf = 64.5mhz uhf phase noise vs. offset frequency offset frequency (khz) uhf phase noise (dbc/hz) max3542 toc19 -130 -120 -110 -100 -90 -80 -70 -60 0.1 1 10 100 1000 f rf = 801mhz ifout1_ normalized frequency response (5mhz to 200mhz) frequency (mhz) ifout1_ power (dbm) max3542 toc20 -20 -15 -10 -5 0 5 1 10 100 1000
max3542 complete single-conversion television tuner 8 _______________________________________________________________________________________ ifvga voltage gain vs. ifagc voltage ifagc voltage (v) ifvga voltage gain (db) max3542 toc21 0.5 1.0 1.5 2.0 2.5 3.0 10 20 30 40 50 60 +25 c -40 c +85 c ifvga im3 vs. ifagc voltage ifagc voltage (v) ifvga im3 (dbc) max3542 toc22 input power (dbm) -80 -60 -40 -20 0.5 1.0 1.5 2.0 2.5 3.0 -60 -50 -40 -30 -20 p in v out = 1.5 v p-p im3 pin description typical operating characteristics (continued) (max3542 ev kit, v cc = +3.3v, v ifagc = 3.0v, v rfagc = 3.0v, t a = +25c, unless otherwise noted.) pin name function 1 scl 2-wire serial-clock interface. requires a pullup resistor to v cc . 2 sda 2-wire serial-data interface. requires a pullup resistor to v cc . 3, 10, 23, 28, 32, 33, 37, 41, 44 v cc power-supply connections. bypass each supply pin to ground with a 1000pf capacitor. 4 uhf_in uhf rf input. requires a dc-blocking capacitor. 5 vhf_in vhf rf input. requires a dc-blocking capacitor. 6 rfgnd2 rf ground. bypass to the pcbs ground plane with a 1000pf capacitor. do not connect rfgnd2 and rfgnd3 together. 7 lext rf vga supply voltage. connect through a 270nh pullup inductor to v cc . 8 rfgnd3 rf ground. bypass to the pcbs ground plane with a 1000pf capacitor. do not connect rfgnd2 and rfgnd3 together. 9 rfagc rf v g a g ai n c ontr ol v ol tag e. accep ts a d c vol tag e fr om 0.5v ( m i ni m um g ai n) to 3v ( m axi m um g ai n) . 11C22, 27, 31 gnd ground. connect to the pcbs ground plane. 24 ifout2- inver ti ng if v g a outp ut. c onnect to the i np ut of an anti - al i asi ng fi l ter . req ui r es a d c - b l ocki ng cap aci tor . 25 ifout2+ n oni nver ti ng if v ga o utp ut. c onnect to the i np ut of an anti - al i asi ng fi l ter . req ui r es a d c - b l ocki ng cap aci tor . 26 ifagc if vga gain control voltage. accepts a dc voltage from 0.5v (minimum gain) to 3v (maximum gain). 29 ifin- inverting if vga input. connect to the output of an if-saw filter. 30 ifin+ noninverting if vga input. connect to the output of an if-saw filter. 34 ifovld if overload detector open-collector output. requires a 10k pullup resistor to v cc . 35 ifout1+ noninverting if lna output. requires a dc-blocking capacitor. 36 ifout1- inverting if lna output. requires a dc-blocking capacitor. 38 ldo vco ldo bypass. bypass to ground with a 0.47f capacitor.
max3542 complete single-conversion television tuner _______________________________________________________________________________________ 9 pin name function 39 gnd_tune vtune ground connection. connect to the pcb ground plane. all loop filter component gnds must be connected to this pin (see the typical application circuit ). 40 vtune vco tuning input. connect to the pll loop filter output. 42 mux test output. leave this pin unconnected during normal operation. 43 cp charge-pump output. connect to pll loop filter input. 45 xtaln crystal oscillator feedback. see the typical application circuit. 46 xtalp crystal oscillator feedback. see the typical application circuit. 47 addr1 2-wire serial-interface address line 1. this pin along with addr2 sets the device address for the i 2 c-compatible serial interface. 48 addr2 2-wire serial-interface address line 2. this pin along with addr1 sets the device address for the i 2 c-compatible serial interface. ep exposed paddle. internally connected to gnd. solder evenly to the pcb ground plane for proper operation. pin description (continued)
max3542 detailed description register descriptions the max3542 includes 11 programmable registers and two read-only registers. the 11 programmable registers include two n-divider registers, an r-divider register, a vco register, an ifovld/charge pump/filter select register, a control register, a shutdown register, and tracking filter control registers. these 11 programma- ble registers are also readable. the read-only registers include a status register and a rom table data register. recommended default bit settings are provided for user convenience only and are not guaranteed. the user must write all registers after power-up and no earli- er than 100s after power-up. complete single-conversion television tuner 10 ______________________________________________________________________________________ msb lsb data byte register name read/ write register address d7 d6 d5 d4 d3 d2 d1 d0 n-div high both 0x00 0 n14 n13 n12 n11 n10 n9 n8 n-div low both 0x01 n7 n6 n5 n4 n3 n2 n1 n0 r-div both 0x02 0 r6 r5 r4 r3 r2 r1 r0 vco both 0x03 vco4 vco3 vco2 vco1 vco0 ld vdiv1 vdiv0 ifo v ld , c har g e p um p , and fi l ter s el ect both 0x04 0 ifovld2 ifovld1 ifovld0 cp1 cp0 tf1 tf0 control both 0x05 0 0 0 0 shdn _rf shdn _ifvga inpt1 inpt0 shutdown both 0x06 shdn _mix1 shdn _mix0 shdn _if shdn _od shdn _syn 000 tr acki ng fi l ter s er i es c ap aci tor both 0x07 tfs7 tfs6 tfs5 tfs4 tfs3 tfs2 tfs1 tfs0 tracking fi l ter p ar al lel cap acitor both 0x08 fld 0 tfp5 tfp4 tfp3 tfp2 tfp1 tfp0 tracking filter rom address both 0x09 0 0 0 0 tfa3 tfa2 tfa1 tfa0 reserved both 0x0a x x x x x x x x rom table data readback read 0x0b tfr7 tfr6 tfr5 tfr4 tfr3 tfr2 tfr1 tfr0 status read 0x0c por ld2 ld1 ld0 x x x x table 1. register configuration bit name bit location (0 = lsb) recommended default function reserved 7 0 must be set to 0. n[14:8] 6C0 0000001 sets the most significant bits of the pll integer divider (n). default integer divider value is n = 4688. n can range from 256 to 32,767. table 2. n-div high register (address: 0000 b )
max3542 complete single-conversion television tuner ______________________________________________________________________________________ 11 bit name bit location (0 = lsb) recommended default function n[7:0] 7C0 10101011 sets the least significant bits of the pll integer divider (n). default integer divider value is n = 4688. n can range from 256 to 32,767. table 3. n-div low register (address: 0001 b ) bit name bit location (0 = lsb) recommended default function reserved 7 0 must be set to 0. r[6:0] 6C0 0010000 sets the pll reference divider (r). default reference divider value is r = 64. r can range from 16 to 127. table 4. r-div register (address: 0010 b ) bit name bit location (0 = lsb) recommended default function vco[4:3] 7C6 10 vco select. selects one of three possible vcos. 00 = vcos shut down 01 = selects vco1 10 = selects vco2 11 = selects vco3 vco[2:0] 5C3 111 v c o sub - b and sel ect. s el ects one of ei g ht p ossi b l e v c o sub - b and s. 000 = selects sb0 001 = selects sb1 010 = selects sb2 011 = selects sb3 100 = selects sb4 101 = selects sb5 110 = selects sb6 111 = selects sb7 ld 2 1 lock detect enable. 0 = disabled 1 = enabled vdiv[1:0] 1C0 10 vco divider ratio select. 00 = s ets v c o d i vi d er to 4 01 = s ets v co d i vi d er to 8 10 = sets vco divider to 16 11 = sets vco divider to 32 table 5. vco register (address: 0011 b )
max3542 complete single-conversion television tuner 12 ______________________________________________________________________________________ bit name bit location (0 = lsb) recommended default function reserved 7 0 must be set to 0. ifovld[2:0] 6C4 000 write content of rom register od[2:0] to this location. cp[1:0] 3C2 00 selects the typical charge-pump current. 00 = 0.5ma 01 = 1ma 10 = 1.5ma 11 = 2ma tf[1:0] 1C0 00 selects the tracking filter band of operation. 00 = vhf_lo 01 = vhf_hi 10 = uhf 11 = factory use only table 6. ifovld, charge pump, and filter select register (address: 0100 b ) bit name bit location (0 = lsb) recommended default function reserved 7C4 0000 must be set to 0000. shdn_rf 3 0 rf shutdown. 0 = rf circuitry enabled 1 = rf circuitry disabled s h dn _ifv ga 2 0 if vga shutdown. 0 = if vga enabled 1 = if vga disabled inpt[1:0] 1C0 01 selects the rf input. 00 = selects vhf_in, lpf enabled 01 = selects vhf_in, lpf disabled 10 = selects uhf_in 11 = factory use only table 7. control register (address: 0101 b ) bit name bit location (0 = lsb) recommended default function shdn_mix [1:0] 7C6 00 mixer shutdown. 00 = mixer enabled 01,10 = factory use only 11 = mixer disabled shdn_if 50 if shutdown. 0 = if section enabled 1 = if section disabled shdn_od 40 ifovld shutdown. 0 = power detector enabled 1 = power detector disabled shdn_syn 30 frequency synthesizer shutdown. 0 = synthesizer enabled 1 = synthesizer disabled reserved 2C0 000 must be set to 000. table 8. shutdown register (address: 0110 b )
max3542 complete single-conversion television tuner ______________________________________________________________________________________ 13 bit name bit location (0 = lsb) recommended default function tfs[7:0] 7C0 00001111* programs series capacitor values in the tracking filter. table 9. tracking filter series capacitor register (address: 0111 b ) *see the rf tracking filter section. bit name bit location (0 = lsb) recommended default function tfr[7:0] 7C0 00000000* tracking filter data bits read from the devices rom table. table 13. rom table data readback register (address: 1011 b ) *see the rf tracking filter section. bit name bit location (0 = lsb) recommended default function reserved 7C0 n/a reserved. do not program these bits during normal operation. table 12. reserved register (address: 1010 b ) *see the rf tracking filter section. *see the rf tracking filter section. bit name bit location (0 = lsb) recommended default function fld 7 0 filter load bit. a 0 to 1 transition of this bit forces the loading of the rom table data readback register. reserved 6 0 must be set to 0. tfp[5:0] 5C0 001001* programs parallel capacitor values in the tracking filter. table 10. tracking filter parallel capacitor register (address: 1000 b ) bit name bit location (0 = lsb) recommended default function reserved 7C4 0000 must be set to 0000. tfa[3:0] 3C0 0000* address bits of the rom register to be read. table 11. tracking filter rom address register (address: 1001 b ) bit name bit location (0 = lsb) recommended default function por 7 n/a power-on reset. 0 = status register has been read 1 = power reset since last status register read ld[2:0] 6C4 n/a vco tuning voltage indicators. 000 = pll not in lock, tune to the next lowest sub-band 001C110 = pll in lock 111 = pll not in lock, tune to the next higher sub-band reserved 3C0 n/a reserved. table 14. status register (address: 1100 b )
max3542 2-wire serial interface the max3542 uses a 2-wire i 2 c-compatible serial inter- face consisting of a serial-data line (sda) and a serial- clock line (scl). sda and scl facilitate bidirectional communication between the max3542 and the master at clock frequencies up to 400khz. the master initiates a data transfer on the bus and generates the scl signal to permit data transfer. the max3542 behaves as a slave device that transfers and receives data to and from the master. pull sda and scl high with external pullup resistors (1k or greater) for proper bus operation. one bit is transferred during each scl clock cycle. a minimum of nine clock cycles is required to transfer a byte in or out of the max3542 (8 data bits and an ack/nack). the data on sda must remain stable during the high period of the scl clock pulse. changes in sda while scl is high and stable are considered control sig- nals (see the start and stop conditions section). both sda and scl remain high when the bus is not busy. start and stop conditions the master initiates a transmission with a start condi- tion (s), which is a high-to-low transition on sda while scl is high. the master terminates a transmission with a stop condition (p), which is a low-to-high transition on sda while scl is high. acknowledge and not-acknowledge conditions data transfers are framed with an acknowledge bit (ack) or a not-acknowledge bit (nack). both the mas- ter and the max3542 (slave) generate acknowledge bits. to generate an acknowledge, the receiving device must pull sda low before the rising edge of the acknowledge-related clock pulse (ninth pulse) and keep it low during the high period of the clock pulse. to generate a not-acknowledge condition, the receiver allows sda to be pulled high before the rising edge of the acknowledge-related clock pulse, and leaves sda high during the high period of the clock pulse. monitoring the acknowledge bits allows for detection of unsuccessful data transfers. an unsuccessful data transfer happens if a receiving device is busy or if a system fault has occurred. in the event of an unsuc- cessful data transfer, the bus master must reattempt communication at a later time. slave address the max3542 has a 7-bit slave address that must be sent to the device following a start condition to initi- ate communication. the slave address is determined by the state of the addr2 and addr1 pins and is equal to 11000[addr2][addr1]. the 8th bit (r/ w ) fol- lowing the 7-bit address determines whether a read or write operation occurs. table 15 shows the possible address configurations. the max3542 continuously awaits a start condition followed by its slave address. when the device recog- nizes its slave address, it acknowledges by pulling the sda line low for one clock period; it is ready to accept or send data depending on the r/ w bit (figure 1). complete single-conversion television tuner 14 ______________________________________________________________________________________ scl sda 123456789 s 1 1 0 0 0 addr2 addr1 r/w ack slave address p note: timing parameters conform with i 2 c bus specifications. figure 1. max3542 slave address byte addr2 addr1 write address read address 0 0 0xc0 0xc1 0 1 0xc2 0xc3 1 0 0xc4 0xc5 1 1 0xc6 0xc7 table 15. max3542 address configurations
write cycle when addressed with a write command, the max3542 allows the master to write to a single register or to multi- ple successive registers. a write cycle begins with the bus master issuing a start condition followed by the seven slave address bits and a write bit (r/ w = 0). the max3542 issues an ack if the slave address byte is successfully received. the bus master must then send to the slave the address of the first register it wishes to write to. if the slave acknowledges the address, the master can then write one byte to the register at the specified address. data is written beginning with the most significant bit. the max3542 again issues an ack if the data is suc- cessfully written to the register. the master can contin- ue to write data to the successive internal registers with the max3542 acknowledging each successful transfer, or it can terminate transmission by issuing a stop con- dition. the write cycle does not terminate until the mas- ter issues a stop condition. figure 2 illustrates an example in which registers 0 through 2 are written with 0x0e, 0xd8, and 0xe1, respectively. read cycle a read cycle begins with the bus master issuing a start condition followed by the seven slave address bits and a write bit (r/ w = 0). the max3542 issues an ack if the slave address byte is successfully received. the master then sends the 8-bit address of the first register that it wishes to read. the max3542 then issues another ack. next, the master must issue a start condition followed by the seven slave address bits and a read bit (r/ w = 1). the max3542 issues an ack if it successfully recognizes its address and begins sending data from the specified register address starting with the most significant bit (msb). data is clocked out of the max3542 on the rising edge of scl. on the 9th rising edge of scl, the master can issue an ack and continue reading successive regis- ters or it can issue a nack followed by a stop condi- tion to terminate transmission. the read cycle does not terminate until the master issues a stop condi- tion. figure 3 illustrates an example in which registers 0 and 1 are read back. max3542 complete single-conversion television tuner ______________________________________________________________________________________ 15 start write device address r/w 11000[addr2][addr1] 0 write register address 0x00 ack ack ack ack ack write data to register 0x00 0x0e write data to register 0x01 0xd8 write data to register 0x02 0xe1 stop figure 2. example: write registers 0 through 2 with 0x0e, 0xd8, and 0xe1, respectively start write device address r/w 11000[addr2][addr1] write device address 11000[addr2][addr1] 0 write 1st register address 0x00 ack nack ack read data reg 0 d7Cd0 stop r/w 1 ack read data reg 1 d7Cd0 ack start figure 3. example: read data from registers 0 and 1
max3542 applications information rf inputs the max3542 features separate uhf and vhf inputs that are matched to 75 . both inputs require a dc- blocking capacitor. the active inputs are selected by the input registers. in addition, the input registers enable or disable the lowpass filter, which can be used when the vhf input is selected. for 47mhz to 100mhz, select the vhf_in with the lpf filter enabled (inpt = 00). for 100mhz to 326mhz, select vhf_in with lpf disabled (inpt = 01). for 326mhz to 862mhz, select uhf_in (inpt = 10). the separate vhf and uhf inputs can be driven from a single rf source using a diplex filter. for diplex filter schematic and component values, refer to the max3542 evaluation kit data sheet. rf gain control the gain of the rf lna can be adjusted over a typical range of 45db with the rfagc pin. the rfagc input accepts a dc voltage from 0.5v to 3v, with 3v provid- ing maximum gain. this pin can be controlled with the if power-detector output to form a closed rf gain-con- trol loop. see the closed-loop rf gain control section for more information. rf tracking filter the max3542 includes a programmable tracking filter for each band of operation to optimize rejection of out-of-band interference while minimizing insertion loss for the desired received signal. the center fre- quency of each tracking filter is selected by a switched-capacitor array that is programmed by the tfs[7:0] bits in the tracking filter series capacitor register and the tfp[5:0] bits in the tracking filter parallel capacitor register. optimal tracking filter settings for each channel vary from part to part due to process variations. to accom- modate part-to-part variations, each part is factory cali- brated by maxim. during calibration, the y-intercept and slope for the series and parallel tracking capacitor arrays are calculated and written into an internal rom table. the user must read the rom table upon power- up and store the data in local memory (8 bytes total) to calculate the optimal tfs[7:0] and tfp[5:0] settings for each channel. table 16 shows the address and bits for each rom table entry. see the interpolating tracking filter coefficients section for more information on how to calculate the required values. reading the rom table each rom table entry must be read using a two-step process. first, the address of the rom bits to be read must be programmed into the tfa[3:0] bits in the tracking filter rom address register (table 11). once the address has been programmed, the data stored in that address is transferred to the tfr[7:0] bits in the rom table data readback register (table 13). the rom data at the specified address can then be read from the tfr[7:0] bits and stored in the micro- processors local memory. complete single-conversion television tuner 16 ______________________________________________________________________________________ msb lsb data byte description address d7 d6 d5 d4 d3 d2 d1 d0 reserved 0x0 od[2] od[1] od[0] x x x x x vhf low 0x1 ls0[5] ls0[4] ls0[3] ls0[2] ls0[1] ls0[0] ls1[3] ls1[2] vhf low 0x2 ls1[1] ls1[0] lp0[5] lp0[4] lp0[3] lp0[2] lp0[1] lp0[0] vhf low vhf high 0x3 lp1[3] lp1[2] lp1[1] lp1[0] hs0[5] hs0[4] hs0[3] hs0[2] vhf high 0x4 hs0[1] hs0[0] hs1[3] hs1[2] hs1[1] hs1[0] hp0[5] hp0[4] vhf high 0x5 hp0[3] hp0[2] hp0[1] hp0[0] hp1[3] hp1[2] hp1[1] hp1[0] uhf 0x6 us0[5] us0[4] us0[3] us0[2] us0[1] us0[0] us1[5] us1[4] uhf 0x7 us1[3] us1[2] us1[1] us1[0] up0[5] up0[4] up0[3] up0[2] uhf 0x8 up0[1] up0[0] up1[5] up1[4] up1[3] up1[2] up1[1] up1[0] table 16. rom table
interpolating tracking filter coefficients the tfs[7:0] and tfp[5:0] bits must be reprogrammed for each channel frequency to optimize performance. the optimal settings for each channel can be calculat- ed from the rom table data using the equations below: analog (pal) channels: vhf_lo filter: vhf_hi filter: : uhf filter: where: f rf = operating frequency in megahertz. tfs = decimal value of the optimal tfs[7:0] setting (table 9) for the given operating frequency. tfp = decimal value of the optimal tfp[5:0] setting (table 10) for the given operating frequency. ls0, ls1, lp0, lp1, hs0, hs1, hp0, hp1, us0, us1, up0, and up1 = the decimal values of the rom table coefficients (table 16). digital (dvb-t) channels: consult the factory for dvb-t coefficients. if overload detector the max3542 includes a broadband if overload detec- tor, which provides an indication of the total power pre- sent at the rf input. the overload-detector output voltage is compared to a reference voltage, and the difference is amplified. this error signal drives an open-collector tran- sistor whose collector is connected to the ifovld pin, causing the ifovld pin to sink current. the nominal full- scale current sunk by the ifovld pin is 300a. the ifovld pin requires a 10k pullup resistor to v cc . the if overload detector is calibrated at the factory to attack at 0.7v p-p at the ifout1. upon power-up, the baseband processor must read od[2:0] from the rom table and store it in the ifovld register. closed-loop rf gain control closed-loop rf gain control can be implemented by connecting the ifovld output to the rfagc input. using a 10k pullup resistor on the ifovld pin as shown in the typical application circuit results in a nominal control voltage range of 0.5v to 3v. vco and vco divider selection the max3542 frequency synthesizer includes three vcos and eight vco sub-bands to guarantee a 2200mhz to 4400mhz vco frequency range. the fre- quency synthesizer also features an additional vco frequency divider that must be programmed to either 4, 8, 16, or 32 by the vdiv[1:0] bits in the vco register based on the channel being received. to ensure pll lock, the proper vco and vco sub- band for the channel being received must be chosen by iteratively selecting a vco and vco sub-band, then reading the ld[2:0] bits to determine if the pll is locked. any reading from 001 to 110 indicates the pll is locked. if ld[2:0] reads 000, the pll is unlocked and the selected vco is at the bottom of its tuning range; a lower vco sub-band must be selected. if ld[2:0] reads 111, the pll is unlocked and the selected vco is at the top of its tuning range; a higher vco sub-band must be selected. the vco and vco sub-band settings should be progressively increased or decreased until the ld[2:0] reading falls in the 001 to 110 range. due to overlap between vco sub-band frequencies, it is possible that multiple vco settings can be used to tune to the same channel frequency. system per- formance at a given channel should be similar between the various possible vco settings, so it is sufficient to select the first vco and vco sub-band that provides lock. layout considerations the max3542 ev kit can serve as a guide for pcb lay- out. keep rf signal lines as short as possible to mini- mize losses and radiation. use controlled impedance on all high-frequency traces. the exposed paddle must be soldered evenly to the boards ground plane for proper operation. use abundant vias beneath the exposed pad- dle for maximum heat dissipation. use abundant ground vias between rf traces to minimize undesired coupling. to minimize coupling between different sections of the ic, the ideal power-supply layout is a star configuration, which has a large decoupling capacitor at the central v cc node. the v cc traces branch out from this node, with each trace going to separate v cc pins of the max3542. each v cc pin must have a bypass capacitor with a low impedance to ground at the frequency of interest. do not share ground vias among multiple con- nections to the pcb ground plane. tfs 10 [( us0 64 +3) (2 us1 64 -3) = + int[ f f10] [(0.8 up0 64 + rf -3 -20 tfp int[10 = ] 1 1.6) (2 up1 64 -2.5) f 10 ] rf -3 ]-1 + 0 0 tfs 10 [(1.3 hs0 64 +2.5) (4 hs1 16 = + int[ -8) f 10 ] [(0.8 hp rf -3 tfp int[10 ? = ]10 0 0 64 +1.6) (1.6 hp1 16 -3.2) f 10 rf + - -3 ] ] t fs 10 [(1.1 ls0 64 +2.2) (4 ls1 16 = + int[ - 12) f 10 ] [(0.8 lp rf -3 t fp int[10 ? = ]10 0 0 64 +1.6) (8 lp1 16 - 14) f 10 ] rf -3 ] + max3542 complete single-conversion television tuner ______________________________________________________________________________________ 17
max3542 complete single-conversion television tuner 18 ______________________________________________________________________________________ typical application circuit max3542 36 ifout1- 1 13 48 + 14 47 15 46 16 45 17 44 18 43 19 42 20 41 21 40 22 39 23 38 24 37 scl 35 ifout1+ 2 sda 34 ifovld 3 v cc 33 v cc 4 uhf_in 32 v cc v ref 5 vhf_in 31 gnd 6 rfgnd2 30 ifin+ 7 lext 29 ifin- 8 rfgnd3 28 v cc 9 rfagc 27 gnd 10 v cc 26 ifagc 11 gnd 25 ifout2+ 12 gnd 1000pf addr2 gnd addr1 gnd xtalp gnd xtaln gnd v cc gnd cp gnd mux gnd v cc gnd vtune gnd gnd_tune gnd ldo v cc v cc ifout2- serial interface r pd cp n vco divider anti-aliasing filter 2.7k ep + - ifout+ v ifagc ifout- ifovld v cc 0.1 f 1000pf 10 10 0.1 f v cc 1000pf 10k v cc 1000pf v cc 1000pf v cc 1000pf 1000pf 2.7k 2.7k 2.7k ifovld 0.1 f 1000pf 47 f 100 820pf 560pf 0.033 f 2.2k v cc if-saw filter 1000pf 1000pf 22pf 8mhz 4.3k 220pf 220pf 270nh 1000pf v cc v cc sdata sclk address 2 address 1 v cc v cc v cc ** ** ** ** 1000pf v cc **connect to common ground point at pin 39. chip information process: bicmos
max3542 complete single-conversion television tuner ______________________________________________________________________________________ 19 package information for the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages . note that a +, #, or - in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing per - tains to the package regardless of rohs status. package type package code outline no. land pattern no. 48 lga-ep l4877a+1 21-0157 90-0302
max3542 complete single-conversion television tuner maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 20 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ? 2011 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. revision history revision number revision date description pages changed 0 10/07 initi al rel ease 1 12/07 correct toc 01 graph and a few er ror s 1, 2, 5, 7 24/11 added soldering temperature and corrected lead temperature in the absolute maximum ratings 2

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